1. Field of the Invention
The present invention relates to the structure of a semiconductor integrated circuit and a method of changing the structure by modifying just one mask used to define a metal interconnection layer, thereby altering the logic functions of the integrated circuit.
2. Description of the Related Art
The need to alter the logic of an integrated circuit arises sometimes because of a change in specifications during the design stage, sometimes because of the discovery of faults during functional tests in the manufacturing stage, and sometimes for various other reasons. Such alterations are time-consuming and expensive because they require the layout of the circuit to be changed.
The basic problem is illustrated in FIG. 1, which is a simplified plan view of part of a conventional integrated circuit. The hatched regions 10, 12, 14 are patterns in a metal layer overlying a semiconductor substrate. Power is supplied at the power supply potential (VDD) from a metal power supply pattern 10, and at the ground potential (VSS) from a metal ground pattern 14, to a first functional block A disposed in a first region 16 and a second functional block B disposed in a second region 18. A signal output from the first functional block A is directly input to the second functional block B through a metal pattern 12. If the logic of this signal needs to be inverted because of a problem discovered after the circuit layout has been completed, or after functional testing has been completed, it becomes necessary to insert an inverter cell, comprising a p-channel metal-oxide-semiconductor (PMOS) transistor and an n-channel metal-oxide-semiconductor (NMOS) transistor, between blocks A and B, but blocks A and B have been laid out close together, as is normal, and there is not enough space between them to accommodate the additional transistors. Accordingly, in order to insert the inverter cell, blocks A and B must be relocated to widen the space between them, possibly requiring other circuit blocks to be moved as well. In the worst case, the layout of the entire integrated circuit has to be redesigned. In any case, to relocate blocks A and B, all of the photolithography masks used in the integrated circuit fabrication process must be altered, an expensive and time-consuming process.
Japanese Unexamined Patent Application Publication No. H07-130858 discloses a method of simplifying such alterations by designing extra diffusion regions and gate terminals into a cell-based integrated circuit, below the metal power and ground patterns outside the cells, so that transistors and logic gates can be added, if necessary, without changing the cell layout. This type of alteration, however, requires the addition of new signal lines, so it is still necessary to modify at least two photolithography masks: one mask used to define an interconnection pattern in a metal interconnection layer, and another mask used to define a contact hole pattern (or a through hole pattern) in a dielectric layer.
Patent Cooperation Treaty Patent Application Publication No. WO00/05764 discloses a so-called master-slice method in which a wafer of semiconductor integrated circuits is processed up to the stage in which metal interconnections are formed, and then the interconnections, protective layers, and so on are formed according to user specifications in such a way that signal lines are not routed over power and ground lines. A design change therefore affects only the metal interconnection layers, but a change such as the insertion of an inverter still requires the modification of at least two photolithography masks and may require extensive layout changes as described above.
It would be desirable for simple design changes, such as the insertion of an inverter, to be made by simple modifications to a single photolithography mask, without requiring any changes in the layout of existing circuit blocks.